Compensation of offset drift with temperature for operational amplifiers

ABSTRACT

A method and apparatus for compensating for offset and drift of offset in an amplifier circuit having metal oxide semiconductor transistors in an input stage thereof and including a node responsive to a bias to change the offset of the amplifier circuit. In one embodiment, an offset digital-to-analog converter provides a first programmable bias corresponding to an offset of the amplifier circuit. A drift digital-to-analog converter provides a second programmable bias corresponding to a drift of the offset of the amplifier circuit. The first programmable bias and the second programmable bias are combined and coupled to the node. In another embodiment, a first programmable offset/drift generator is provided, capable of sourcing a first bias to the amplifier node compensating for a first portion of the offset and a first portion of the drift of the offset of the amplifier circuit. A second programmable offset/drift generator is provided, capable of sourcing a second bias to the amplifier node compensating for a second portion of the offset and a second portion of the drift of the offset of the amplifier circuit, wherein the rate of drift compensation with temperature of the second bias is different from the rate of compensation of the second bias. By suitable programming of the first and second programmable offset/drift generators the compensation of the offset and the offset of the drift of the amplifier circuit may be optimized.

This application claims priority under 35 USC § 119(e)(1) of provisionalapplication Ser. No. 60/437,598, filed Dec. 31, 2002.

TECHNICAL FIELD OF THE INVENTION

This invention relates to operational amplifiers and circuits that usethem, and more particularly relates to a method and apparatus forcompensating for offset and the drift of input offset with temperature.

BACKGROUND OF THE INVENTION

Operational amplifiers, or, “op-amps,” are well-known circuits used in avariety of applications. For example, operational amplifiers are used asactive filters, oscillators, voltage and current amplifiers, integratorsand differentiators, analog-to-digital converters (“ADCs”) anddigital-to-analog converters (“DAC's”), to name a few. Desirablecharacteristics of op-amps include high open loop gain, high inputimpedance, low output impedance low offset and low offset drift.

However, one problem op-amps suffer is called “offset error.” Thiseffect occurs because of the inherent lack of precision in the matchingof the op-amp's components, including the two differential inputtransistors. Ideally, the op-amp has a zero output voltage for zeroinput voltage. But, when the op-amp's input transistors are unmatched,the op-amp may have a non-zero output voltage for zero input, which isthe offset error. The voltage applied to the differential input thatmakes the output voltage zero is called the “input offset voltage.” Thisoffset error can have an adverse effect in any circuit in which theop-amp is used, if compensation is not provided for it.

In precision applications, it is necessary for the offset error to beminimized, and numerous approaches to that problem have been proposedand implemented. However, even after compensating for the offset error,the factors giving rise to it can vary with varying temperature, givingrise to a variation in the offset error with temperature, called “offsetdrift.” This offset drift can make compensation for offset error that isstatic with respect to temperature inadequate in precision applications.

Approaches to compensate for offset drift have therefore been proposed.One approach is disclosed in U.S. Pat. No. 6,396,339, which issued toKarl H. Jacobs on May 28, 2002, and was assigned to Texas InstrumentsIncorporated. In the technique disclosed therein, input offset voltageis compensated by balancing the operational amplifier over the operatingtemperature range after the device has been initially trimmed. Theiroperational amplifier employs a lower input offset voltage, whichremains low over the operating temperature range without a separatetemperature compensation circuit. They provide a separate trim devicefor each current path of the circuit to maintain symmetry. Thus, thecurrent paths of the differential circuit have the same leakage currentupon temperature excursions. Ideally, the leakage current will occur inboth current paths of the differential circuit and maintain circuitbalance.

Another example is disclosed in U.S. Pat. No. 4,490,713, which issued toAndrij Mrozowski et al. on Dec. 25, 1984, and was assigned to Burr-BrownInc. In the technique disclosed therein, a solution to offset drift isdescribed in the context of an ADC having offset drift, a portion ofwhich may be contributed by an operational amplifier therein. Theyemploy a differential temperature sensor that generates atemperature-dependent voltage, Vt. During calibration at ambienttemperature, that voltage is applied to the ADC input to obtain asixteen-bit digital representation of Vt, which is stored. Then, in use,after an analog sample is converted the differential temperature sensoris applied to the input again, to obtain another sixteen-bit digitalrepresentation of Vt for whatever the present temperature is. Thedifference between the two values is used to do a look-up in a gain andoffset drift storage register, which is preprogrammed to contain theamount of gain and offset drift that occurs as a function of temperaturechange. The sixteen-bit digital representation of the analog sample iscompensated by that amount to obtain the final digital value for theanalog sample.

It is therefore desirable to have an op-amp including compensation foroffset drift that is effective over an intended temperature range, whileat the same time offering a minimal performance penalty for the op-amp.

SUMMARY OF THE INVENTION

In accordance with the present invention there is provided a method andapparatus for compensating for offset and drift of offset in anamplifier circuit having metal oxide semiconductor transistors in aninput stage thereof and including a node responsive to a bias to changethe offset of the amplifier circuit. In one embodiment, an offsetdigital-to-analog converter provides a first programmable biascorresponding to an offset of the amplifier circuit. A driftdigital-to-analog converter provides a second programmable biascorresponding to a drift of the offset of the amplifier circuit. Thefirst programmable bias and the second programmable bias are combinedand coupled to the node. In another embodiment, a first programmableoffset/drift generator is provided, capable of sourcing a first bias tothe amplifier node compensating for a first portion of the offset and afirst portion of the drift of the offset of the amplifier circuit. Asecond programmable offset/drift generator is provided, capable ofsourcing a second bias to the amplifier node compensating for a secondportion of the offset and a second portion of the drift of the offset ofthe amplifier circuit, wherein the rate of drift compensation withtemperature of the second bias is different from the rate ofcompensation of the second bias. By suitable programming of the firstand second programmable offset/drift generators the compensation of theoffset and the offset of the drift of the amplifier circuit may beoptimized.

These and other features of the invention will be apparent to thoseskilled in the art from the following detailed description of theinvention, taken together with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an operational amplifier having offsetcompensation.

FIG. 2 is a diagram of a pertinent portion of the operational amplifierof FIG. 1.

FIG. 3 is a diagram of the offset DAC of FIG. 1.

FIG. 4 is a diagram of an operational amplifier having offsetcompensation and offset drift compensation.

FIG. 5 is a diagram of the drift DAC of FIG. 4.

FIG. 6 is a diagram of a pertinent portion of the operational amplifierof FIG. 4.

FIG. 7 is a flow chart for a method in accordance with the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The numerous innovative teachings of the present invention will bedescribed with particular reference to the presently preferred exemplaryembodiments. However, it should be understood that this class ofembodiments provides only a few examples of the many advantageous usesand innovative teachings herein. In general, statements made in thespecification of the present application do not necessarily delimit theinvention, as set forth in different aspects in the various claimsappended hereto. Moreover, some statements may apply to some inventiveaspects, but not to others.

An effective approach to offset compensation is shown in FIG. 1. Inthis, a conventional Op-Amp 1 is configured as an amplifier to amplifyan input voltage Vin to generate an output voltage Vout, with resistorsR₁ and R₂ determining the overall gain of the circuit by the well-knownformula:${gain} = {\frac{Vout}{Vin} = {\frac{\left( {{R1} + {R2}} \right)}{R1}.}}$

To compensate for offset error, a programmable offset DAC 2 is provided,that provides a programmable differential offset current bias,comprising positive component ioffset+ and negative component ioffset−.These are programmably adjustable by the application of a digitaladjustment value b<7:0>. By varying the value of b, which may be doneunder control of a program running on a microprocessor, for example, themagnitude of the differential offset current bias can be correspondinglyvaried.

The type of compensation shown in FIG. 1 is known to be effective forop-amps using bipolar technology. For bi-polar process technology, it iswell known that correcting the offset error can at the same time correctfor the offset drift. See, for example, Analysis and Design of AnalogIntegrated Circuits, by Paul R. Gray and Robert G. Meyer, John Wiley &Sons, Inc., © 1993, pp. 250-256, 445-458 (esp. pp. 447-453) and 466-470.To cancel offset and drift at the same time for a bipolar op-amp, aprogrammable current as described in the above-mentioned '713 patent canbe added to the differential amplifier output branches, and thisprogrammable current can be mirrored from the bias current source thatprovides the tail current of the differential stage. This schemeprovides similar drift properties between the differential amplifiercurrents and the error correcting (programmable) current, so that offsetand drift are canceled simultaneously.

On the other hand, for op-amps using CMOS input stages, it is also wellknown that providing offset compensation does not provide the driftcompensation that occurs in op-amps having bipolar input stages. This isdue to the threshold voltage, Vt, mismatch that is common between theinput stage CMOS transistors. Thus, the compensation approach shown inFIG. 1 will only cancel offset error for op-amps using a CMOS inputstage. However, CMOS input stages are very desirable because theyrequire essentially zero input current. Therefore, a new approach isdesirable for canceling the offset error and the offset drift if op-ampshaving CMOS input stages.

As mentioned above, a differential offset current bias can be providedto an op-amp in a manner intended to compensate for offset error. Thiscan be better understood by reference to FIG. 2, which shows a pertinentportion of op-amp 1, specifically, an input portion. A conventional biasgenerator circuit 3 generates voltage biases and, through PMOS devicesP2, P3, P4 and P5, communicates those voltage biases to PMOS devices P6,P7, P8, P9, P10 and P11, in a conventional current source circuit 4,which, in response to the biases so provided, provides current sourcesfor a conventional folded cascode amplifier circuit 5. Folded cascodeamplifier portion 5 has two parts, a differential input amplifierportion comprising NMOS devices N1 and N2 and PMOS devices P12 and P13,and a high swing current amplifier circuit comprising NMOS devices N3,N4, N5 and N6, providing an output Vfcout to the next stage in theop-amp 1.

The differential offset current biases, ioffset+ and ioffset− areprovided at the sources of devices N5 and N6, respectively, as shown.The output Vfcout is also taken at the source of device N6. These biasescompensate for offset error that would otherwise appear in Vfcout, andwould be propagated to the op-amp output Vout.

FIG. 3 is a circuit diagram of the offset DAC 2 of FIG. 2. The offsetDAC 2 is comprised of eight cells, all of the same construction.Exemplary cell 6 is made of PMOS devices P14 and P15, connected inseries, as shown, with the source of device P14 being connected to thepower supply VDD and the drain of device P14 being connected to thesource of device P15, and with the gate of device P14 receiving avoltage bias signal Vbias1, and the gate of device P15 receiving avoltage bias signal Vbias2. The drain of device P15 is connected to thesource of device P16 and the source of device P17. The gate of deviceP16 receives the fourth bit of b<7:0>, i.e., b<3>, while gate of deviceP17 receives the inverse of the fourth bit of b<7:0>, being inverted byinverter 7. The drain of device P16 provides an output current ioutb,while the drain of device P17 provides an output current lout. The biasvoltages Vbias1 and Vbias2 are fixed, stable biases, and control theamount of cell current provided to devices P16 and P17. Depending onwhether the value of b<3> is a “0” or a “1,” the cell current is eitherprovided as iout or ioutb, respectively.

As mentioned above, the eight cells of offset DAC 2 are all of the sameconstruction. All of their output currents iout are summed, as are allof their output currents ioutb, to generate output currents IOUT andIOUTB, respectively, which are the same currents, ioffset+ and ioffset−,respectively, provided to Op-Amp 1. Each cell receives voltage biassignals Vbias1 and Vbias2, as described above in connection with cell 6.However, each cell receives a different bit of b<7:0>, with the firstcell receiving bit b<0>, the second cell receiving bit b<1>, the thirdcell receiving bit b<2>, etc. In addition, the sizes of the devicescorresponding to devices P16 and P17 in cell 6 are scaled so as toprovide a different amount of cell current, one cell compared to thenext. For example, the devices may be scaled so that the second cellprovides twice the amount of cell current as the first cell, the thirdcell provides twice the amount of cell current as the second cell, etc.,in binary fashion. Assuming that bit b<0>is the least significant bit(LSB) of b and bit b<7> is the most significant bit (MSB) of b, givensuch scaling the output currents, the output currents IOUT and IOUTB canbe controlled in binary fashion simply by setting the programmable valueb to the appropriate value. By selecting b to be a two's complementvalue, the mid-point of the range of output currents IOUT and IOUTB canbe made to correspond to a value of b of “0.”

By selecting Vbias1 and Vbias2 to provide a total cell current, for atwo's complement value of b=0, at approximately the anticipated outputcurrents IOUT and IOUTB to compensate an op-am such as op-amp 1 (FIGS. 1and 2) for offset error, the actual offset error for a specific Op-Ampcan be significantly reduced by “fine tuning” the output currents IOUTand IOUTB by selection of the appropriate value of b for that op-amp.Note that while having a binary scaling of current, one cell to thenext, and having b as a two's complement value are advantageousexpedients, other scaling schemes and other valuing schemes for b arepossible.

The offset DAC 2 of FIG. 3 may use the bias generator 3 (FIG. 2) ofop-amp 100 to set its bias voltages Vbias1 and Vbias2. Note also thatthe particular implementation of the offset DAC 2 is exemplary only.Other implementations may be used, for example usingbinary/unary/segmented, push/pull/push-pull configurations, and still bewithin the scope of the invention.

However, even with the provision of an offset DAC as described above inconjunction with FIGS. 1, 2 and 3, the offset compensation so providedis subject to drift with temperature. Therefore, even though a value ofb may be selected to provide greatly reduced offset error at aparticular temperature, if the device is operated at a differenttemperature, the offset error will likely increase because of offsetdrift.

To compensate for such offset drift, a programmable drift DAC 101 isprovided, as shown in FIG. 4. The drift DAC 101 provides a programmabledifferential drift current bias, comprising positive component IOUTd andnegative component IOUTBd. These are programmably adjustable by theapplication of a digital adjustment value a<7:0>. By varying the valueof a, which may be done under control of a program running on amicroprocessor, for example, the magnitude of the differential driftcurrent bias can be correspondingly varied. The currents IOUTd andIOUTBd, respectively, from drift DAC 101 are added to the currents IOUTand IOUTB, respectively, from offset DAC 2, to yield the compensatingcurrents ioffsetd+ and ioffsetd− that are applied to op-amp 100 in amanner similar to that in which ioffset+ and ioffset− are applied toOp-Amp 1 of FIG. 1.

In addition, when the drift compensated compensating currents ioffsetd+and ioffsetd− are selected for optimum drift compensation and applied toOp-Amp 100 as described below, a residual offset may remain in theoutput of Op-Amp 100. In order to compensate for this residual offset, afurther offset compensation is provided, as shown in FIG. 4, by dividingresistor R₁ into resistors R₃ and R₄, and connecting a conventional,programmable current source 102 providing current Ioff to the nodeconnecting resistors R₃ and R₄. The current source needs to providetemperature independent offset. Such a programmable current providingtemperature independent offset can be obtained by a circuit similar tothe circuit shown in FIG. 5. The temperature drift of resistor R₅ inFIG. 5 is cancelled when current is applied as shown in FIG. 4 tosimilar type resistors R₂, R₃, R₄. The current can be mirrored and usedas push-pull fashion also, and can be designed to have binary/unarysegmentation. This type of residual offset correction scheme requiresdrift-matched resistors to be on-chip. Since the residual offsetcorrection will be temperature independent, this programmable currentsource may be used to replace the offset-DAC shown in FIG. 4.

Drift DAC 101 is shown in detail in FIG. 5. In the right of the figurecan be seen eight cells. These eight cells are of the same constructionas the eight cells shown in FIG. 3, and their operation is the same.Therefore, description of their construction and operation is notrepeated in detail here, in the interest of brevity and clarity.However, instead of receiving voltage bias signal Vbias1 and Vbias2,each of the cells in drift DAC 101 receives voltage bias signals Vbias2and Vbias3, respectively, as shown. Voltage Vbias2 is appliedexternally, while voltage Vbias3 is generated internally, as will now bedescribed. The voltages generated by the cells are called ioutd andioutbd. When combined, they form the drift compensating currents IOUTdand IOUTBd, respectively.

Drift DAC 101 includes two op-amps 201 and 202. Op-amp 202 is optional.The inverting input of op-amp 201 receives a further stable voltage biasVosd, while its non-inverting input is connected to a first end of aresistor R₅. The output of op-amp 201 is connected to the gate of a PMOSdevice P18 having its source connected to the power supply VDD. Thedrain of device P18 is connected to the source of a PMOS device P19,which has its gate connected to receive voltage Vbias2 and its drainconnected to the first end of resistor R₅. The non-inverting input ofop-amp 202 receives a still further stable voltage bias Vos, while itsinverting input is connected to its output and to the second end ofresistor R₅.

Note that on a data converter utilizing a drifting main op-amp, matchedresistors are available to do the residual offset cancellation shown inFIG. 4 (R₂, R₃, R₄) and FIG. 5 (R₅). However, on a stand-alone op-amp,some of these resistors will be external, and they will not necessarilymatch with the internal resistors or with each other. In other words,the need for external resistors with good matching properties willincrease system cost. This complicates the offset cancellation at alltemperatures for a stand-alone op-amp. To simplify simultaneous offsetand drift cancellation of such stand-alone op-amps, one exemplaryembodiment of the present invention includes a combinationconfiguration, where two DACs source currents to the main op-amp tocancel offset and drift at the same time.

In this arrangement, the roles of the offset DAC and drift DAC areshared by each DAC 2 and 101. The arrangement shown in FIG. 4 is usedand both DACs 2 and 101 use the architecture described in FIG. 5. Theprogrammable current source 102 correcting for the residual offset errorin FIG. 4 is no longer needed, but it could still be used for finetuning.

This arrangement drives a stable current across resistor R₅ of FIG. 5.Resistor R₅ is constructed of a suitable material having a resistancethat varies with temperature in a known way. The basis for selecting theresistance value R5 for resistor R₅ is as follows. In general. for aresistor R_(n) having a resistance Rn and having a drift coefficientDRIFTn, in parts per million per degree Celsius (ppm/° C.), thedependence of Rn on temperature T in degrees Celsius, relative to areference temperature of 25° C., can be expressed as:Rn(T)=Rn(25)+Rn·DRIFTn·(T−25)  Eq.(1)In general, for a typical CMOS process, DRIFTn for polysilicon resistorsmay be approximately 800 ppm/° C., and for metal resistors may be 3000ppm/° C. Thus, a current In through resistor R_(n) due to a voltage Vacross it, may be expressed as:In(T)=V/Rn(T)=(V/Rn(25))·(1/(1+DRIFTn·(T−25)))  Eq.(2)This equation may be linearized using a Taylor expansion around T=25° C.If only the first two terms of the Taylor series are kept, theapproximate temperature dependence of Iref becomes:In(T)=C 1(1+A 1·(T−25))  Eq.(3)where C1 and A1 are Taylor series coefficients depending on V, Rn(25)and DRIFTn. Specifically, C1=V/Rn(25), and A1=−DRIFTn/(676·C1).

Referring now to FIG. 5, and applying the above principles, the currentIOUTd from drift DAC 101 can be expressed as:IOUTd(T)=a·C 1·(1+A 1·((T−25)),  Eq.(4)where a is the digital code applied to drift DAC 101. Referring back nowto FIG. 4, assuming that the offset DAC 2 uses the architecture shown inFIG. 5, and again based on resistor R₅ having a resistance R5 and havinga drift coefficient DRIFT5, IOUT from offset DAC 101 can be expressed inppm/° C. by Taylor series expansion as:IOUT(T)=b·C 2·(1+A 1·((T−25)),  Eq.(5)where b is the digital code applied to offset DAC 2, and where C2 and A2are Taylor series coefficients depending on V, R5′(25) and DRIFT5′,where R5′ and DRIFT5′ are the resistance value and drift coefficient ofthe counterpart resistor R₅′ (not shown) in offset DAC 2 to resistor R₅in drift DAC 101. Specifically, C2=V/R5′(25), and A2=−DRIFT5′/(676·C2).

Now, applying these principles, to correct for the offset error M atT=25° C., one must apply:b=(a·C 1+M)/C 2  Eq.(6)is applied to Drift DAC 101. Therefore, an offset error M of Op-Amp 100may be corrected provided there is a code “b” satisfying Equation (6)for any value “a”. Substituting Equation (6) into Equation (5) andsubtracting IOUTd from IOUT yields: IOUTd−IOUT=((a·C 1·A 1)−(a·C 1·A 2)−(M·A 2))·(T−25) −M.  Eq.(7)Equation (7) shows that the offset error M is corrected at 25° C., withthe code “a” controlling the temperature drift compensation. For anOp-Amp 100 that has a drift characteristic of D Volts/° C., thecancellation factor −D may be expressed as:−D=((a·C 1 ·A 1)−(a·C 1 ·A 2)−(M·A 2))  Eq.(8)ora=(D−M·A 2)/(C 1·(A 2−A 1)).  Eq.(9)Therefore, the offset of Op-Amp 100 at 85° C. may be measured and storedon a chip including the Op-Amp 100, offset DAC 2 and Drift DAC 101. At25° C., the test can be repeated and both the offset at 25° C., i.e., M,and the drift per degree C., i.e., D, can be measured, where:D=(M(85)−M(25))/(85−25).  Eq.(10)Once the values M and D are measured, then the codes “b” and “a” forsimultaneously canceling the offset and drift, respectively, may beexpressed as:a=(D−M·A 2)/(C 1·(A 2−A 1)),  Eq.(11)andb=(a·C 1+M)/C 2.  Eq.(12)From Equation (9) it can be seen that resistors R₅ and R₅′ arepreferably not made of the same material, since they must have differentdrift characteristics.

The

Now, it was mentioned above that when the drift compensated compensatingcurrents ioffsetd+ and ioffsetd− are selected for optimum driftcompensation and applied to Op-Amp 100, a residual offset may remain,and that in order to compensate for this residual offset, a furtheroffset compensation may be provided, as shown in FIG. 4, by dividingresistor R₁ into resistors R₃ and R₄, and connecting a conventional,programmable current source 102 providing current Ioff to the nodeconnecting resistors R₃ and R₄. These resistors may be constructed ofpolysilicon, or any single type of resistor, as is the feedback resistorR₂, which causes the gain factor to remain stable with temperature. Theresulting compensation, for a gain-of-two, noninverting op-amp, can beexpressed as:Vout=2·Vin−R 3·Ioff.  Eq. (13)

Note also that the particular implementation of the drift DAC 101 shownin FIG. 5 is exemplary only. This drift DAC may also be designed to havebinary/unary/segmented, push/pull/push-pull fashions, and still bewithin the scope of the invention. Programmable drift DAC 101 may alsouse any known method of generating temperature dependent bias current.If the bias circuit of op-amp 100 (FIG. 4) uses a temperatureindependent current generation based on a band-gap circuit, then a goodchoice for the drift DAC 101 bias current is PTAT (proportional toabsolute temperature). On the other hand, if the bias circuit of op-amp100 uses a PTAT current generator, the bias current for the drift-DAC ispreferably band-gap based, that is, independent of the temperature. Bothcases will generate programmable drift that changes linearly withtemperature. If nonlinear drift generation is desired, a drift DAC withPTAT-squared current generation could also be used. Numerous designs forgenerating temperature independent, PTAT and PTAT-squared currents areknown in the art, and, for example, may be found in Voltage References:From Diodes to Precision High-Order Bandgap Circuits, by Gabriel AlfonsoRincon-Mora, IEEE, © Sep. 28, 2001 (ISBN: 0471143367).

Note that the particular place in the circuit where the compensatingcurrents are applied to a given amplifier is a matter of design choicewithin the scope of those of ordinary skill in this art area. In fact,when applying the drift compensated compensating currents ioffsetd+ andioffsetd− to the amplifier circuit of FIG. 2, it is considered preferredto apply those compensating currents to the differential input amplifierpart, as shown in FIG. 6, rather than to the folded cascade circuit partshown in FIG. 2. The reason this is considered preferred is because byapplying the drift compensated compensating currents as shown in FIG. 6,it has been found that better drift compensation may be achieved.

Note that while the embodiment shown in FIG. 4 provides differentialcompensation for a differential amplifier, the principles of the presentinvention are equally applicable to single-ended embodiments. In suchembodiments only a single drift compensated compensating current need begenerated, and applied at a single compensation node in the amplifier.In addition, while the compensation used in the embodiment shown in FIG.4 is current compensation, voltage compensation may be provided, aswell. In such embodiments a suitable node or nodes where an amplifiedvoltage signal appears would be selected for application of thecompensating voltages.

A preferred embodiment of the method of the present invention can be setforth as follows, with reference now to FIG. 7. Initially, the offseterror, ε1, of an amplifier requiring compensation is measured at onetemperature, for example room temperature (25° C.), T1 301. The value ofthis offset is encoded and stored in nonvolatile memory 302. The offseterror, ε2, is then measured at another temperature, for example atemperature higher than room temperature, T2 303. Then, the temperaturedrift, D, is calculated 304. Thus,ε1=ε1+D·(T 2−T 1),  Eq. (2)where D is the temperature drift at T1 (e.g., 25° C.), and is expressedin units of volts/degree. Then, the drift DAC 101 (FIG. 4) input codea<7:0> that cancels drift is calculated 305, and the input code b<7:0>that cancels offset is calculated 306. These codes are stored innonvolatile memory 307. Upon initiation of regular operation, thesestored values are loaded into volatile memory for use in providing theactual compensation in accordance with the principles described above.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims.

1. An apparatus for compensating for offset and drift of offset in anamplifier, comprising: an amplifier circuit having metal oxidesemiconductor transistors in an input stage thereof and including a noderesponsive to a bias to change the offset of the amplifier circuit; anoffset digital-to-analog converter providing a first programmable biascorresponding to an offset of the amplifier circuit; and a driftdigital-to-analog converter providing a second programmable biascorresponding to a drift of the offset of the amplifier circuit; thefirst programmable bias and the second programmable bias being combinedand coupled to the node.
 2. A method for compensating for offset anddrift of offset in an amplifier circuit having metal oxide semiconductortransistors in an input stage thereof and including a node responsive toa bias to change the offset of the amplifier circuit, comprising thesteps of: providing a first programmable bias corresponding to an offsetof the amplifier circuit; providing a second programmable biascorresponding to a drift of the offset of the amplifier circuit;combining the first programmable bias and the second programmable biasand coupling the combined biases to the node.
 3. An apparatus forcompensating for offset and drift of offset in an amplifier, comprising:an amplifier circuit having metal oxide semiconductor transistors in aninput stage thereof and including a node responsive to a bias to changethe offset of the amplifier circuit; a first programmable offset/driftgenerator capable of sourcing a first bias to the amplifier nodecompensating for a first portion of the offset and a first portion ofthe drift of the offset of the amplifier circuit; and a secondprogrammable offset/drift generator capable of sourcing a second bias tothe amplifier node compensating for a second portion of the offset and asecond portion of the drift of the offset of the amplifier circuit,wherein the rate of drift compensation with temperature of the secondbias is different from the rate of compensation of the second bias, suchthat by suitable programming of the first and second programmableoffset/drift generators the compensation of the offset and the offset ofthe drift of the amplifier circuit may be optimized.
 4. A method forcompensating for offset and drift of offset in an amplifier circuithaving metal oxide semiconductor transistors in an input stage thereofand including a node responsive to a bias to change the offset of theamplifier circuit, comprising the steps of: providing a firstprogrammable bias to the amplifier node compensating for a first portionof the offset and a first portion of the drift of the offset of theamplifier circuit; and providing a second programmable bias to theamplifier node compensating for a second portion of the offset and asecond portion of the drift of the offset of the amplifier circuit; andcontrolling the rate of drift compensation with temperature of the firstbias and the second bias such that the second bias is different from therate of compensation of the second bias and the compensation of theoffset and the offset of the drift of the amplifier circuit isoptimized.
 5. A method for compensating for offset and drift of offsetin an amplifier circuit having metal oxide semiconductor transistors inan input stage thereof and including a node responsive to a bias tochange the offset of the amplifier circuit, comprising the steps of:measuring a first offset error at a first temperature; storing the firstoffset error in a first memory; measuring a second offset error at asecond temperature; storing the second offset error in the first memory;computing drift and offset at the first temperature, based on the firstoffset error; computing an offset compensation code; storing the offsetcompensation code in a second, non-volatile memory; computing an offsetdrift compensation code; storing the offset drift compensation code inthe second memory; and upon activation of the amplifier circuit:retrieving the offset compensation code and the offset driftcompensation code; responsive to the retrieved offset compensation code,providing a first programmable bias corresponding to an offset of theamplifier circuit; responsive to the retrieved offset drift compensationcode, providing a second programmable bias corresponding to a drift ofthe offset of the amplifier circuit; combining the first programmablebias and the second programmable bias and coupling the combined biasesto the node.